A spiking network is only as useful as the machine that runs it. Because spikes are sparse, asynchronous events rather than dense tensors, the conventional stack of GPUs and dense linear algebra is a poor fit: it must simulate every timestep whether or not anything spiked. This has driven two parallel efforts: purpose-built neuromorphic hardware that computes only when spikes occur, and software frameworks that make spiking networks tractable to build and train. This page surveys both, and the vexed question of how to measure their efficiency fairly.
Neuromorphic Hardware
Neuromorphic chips co-locate memory and computation and communicate through spikes, sidestepping the data-movement bottleneck that dominates the energy budget of conventional processors. Merolla et al. (2014) demonstrated the approach at scale with IBM's TrueNorth: a fully digital, event-driven chip with a million spiking neurons and 256 million synapses that ran a real-time network at roughly 63 mW, though its synapses were configured offline with no on-chip learning.
Intel's Loihi (Davies et al., 2018) added programmable on-chip synaptic plasticity, allowing networks to learn in place; its successor Loihi 2 introduced graded spikes and fully programmable neuron models, and in 2024 Intel assembled 1,152 Loihi 2 chips into Hala Point, a research system of over a billion neurons. A different philosophy underlies the two large European platforms: Manchester's SpiNNaker (Furber et al., 2014) is a massively parallel array of ARM cores that simulates spiking networks digitally in real time, while Heidelberg's BrainScaleS takes an analog, mixed-signal route, physically emulating neuron dynamics on silicon at up to thousands of times biological speed. At the commercial edge, BrainChip's Akida targets always-on low-power inference, and Tsinghua's hybrid Tianjic chip (Pei et al., 2019) runs both spiking and conventional networks on one fabric, controlling a self-balancing bicycle as a demonstration.
| Platform | Type | Scale (per chip) | Notable trait |
|---|---|---|---|
| IBM TrueNorth (2014) | Digital | 1M neurons, 256M synapses | ~63 mW real-time inference; no on-chip learning |
| Intel Loihi 2 (2021) | Digital, async | Up to 1M neurons | Graded spikes, programmable neurons, on-chip learning |
| SpiNNaker (2014) | Digital (ARM cores) | 18 cores/chip; ~1B neurons at full scale | Real-time, packet-switched, highly flexible |
| BrainScaleS-2 | Analog / mixed-signal | 512 neurons, ~131k synapses | ~1000× accelerated physical emulation |
| BrainChip Akida | Digital (commercial) | Edge-scale NPU mesh | Always-on, low-power edge inference |
| Tianjic (2019) | Hybrid | ~40k neurons, 10M synapses | Runs both ANN and SNN workloads on one chip |
Software Frameworks
Simulators fall into two broad camps. The first serves computational neuroscience, prizing biological detail: Brian2 (Stimberg et al., 2019) lets models be written directly as mathematical equations with physical units, NEST targets large networks of point neurons on high-performance clusters, NEURON models detailed cell morphology and ion channels, and Nengo builds functional brain models through the Neural Engineering Framework.
The second camp brings spiking networks into the deep-learning workflow, running on GPUs with automatic differentiation and surrogate gradients. snnTorch (Eshraghian et al., 2023) and SpikingJelly (Fang et al., 2023) are built on PyTorch (the latter with fused CUDA kernels for speed) and are joined by Norse and BindsNET in the same ecosystem. Intel's Lava framework, meanwhile, targets deployment onto Loihi 2. A community-maintained overview of these tools is kept by Open Neuromorphic.
Efficiency and Benchmarking
The appeal of spiking networks is energy efficiency, but measuring it fairly is subtle. The intuition is sound: a conventional neuron performs a multiply-accumulate for every connection on every forward pass, whereas a spiking neuron mostly performs a cheaper accumulate, and only when a spike actually arrives. Dynamic energy therefore scales with spiking activity rather than with a fixed dense workload. The catch is that spiking inference integrates over a number of discrete timesteps: more timesteps generally raise accuracy but multiply both latency and the number of spike operations, so the efficiency advantage survives only when activity is genuinely sparse.
This makes comparison treacherous. An ANN's operation count is fixed by its architecture, while an SNN's depends on measured spike rates, the number of timesteps, the numeric precision, and, crucially, whether it runs on event-driven neuromorphic silicon or on a GPU optimised for dense math. Reported energy ratios vary widely and are easy to bias, a problem the community has begun to address with standardised, hardware-aware benchmarks such as NeuroBench (Yik et al., 2025). The broader lesson, examined further under challenges, is that spiking efficiency is real but conditional: it is a property of the whole algorithm–hardware system, not of spikes alone.